1. Field of the Invention
The present invention relates to the field of electrically erasable programmable read-only memory (EEPROM) devices and, more particularly, to array configurations for the implementation of memory cells that rely on source-side injection for fast programming.
2. Description of the Related Art
Recently, Flash EEPROM memories have gained substantial interest as the best solution for electrically-rewritable high-density nonvolatile data storage. These semiconductor memories combine the high integration density and the high programming speed of EPROMs with the to higher functionality of EEPROMs by offering electrical in-circuit erasability. Typically, Flash memories are distinguished from "classical" EEPROMs by their block (or sector) erase scheme. That is, in a Flash memory, the byte-selective erasability of EEPROMs is sacrificed for the sake of a higher integration density. The possibility exists, however, to divide the memory in different sectors, each of which can be erased separately.
At first, flash memory was introduced to replace program code EPROMs and battery-backed Random Access Memories ("RAMs") in measuring equipment (for calibration, trimming and data storage), in tuners and TV sets (for programmable channel selection), and in microcomputers (for microcode updates). On the other hand, new applications have arisen such as solid-state disks for small computers and Personal Digital Assistants ("PDAs"), program storage for Digital Signal Processing ("DSP") chips and for portable equipment, smart cards, automotive applications (such as fuel injection control and Automatic Breaking Systems ("ABS")) and neural networks. Additionally, a trend has arisen to integrate logic and nonvolatile memory on the same chip to provide embedded memories, which typically require a compromise between performance, density and processing complexity.
Many commercially available flash EEPROM devices (EEPROMs) use Channel Hot Electron Injection ("CHEI") for writing and Fowler-Nordheim (FN) tunneling through a thin oxide for erasure, although various alternative programming mechanisms have been proposed and implemented. Several classes of flash EEPROM are known.
One class of flash EEPROMs, referred to as "stacked gate" devices, are based on ETOX technology. FIG. 1 illustrates one such device, by way of example. In a stacked gate cell, the floating gate overlies the whole channel area from above the source region to above the drain region, and a single external control gate is arranged on top of the floating gate. After floating gate formation, a high quality dielectric layer (usually oxide-nitrideoxide (ONO)) is deposited to serve as an interpoly dielectric. Alternatively, this interpoly layer could be defined together with the first (and eventually the second) polysilicon layer in a stacked etch process. Stacked gate flash EEPROMs use CHEI at the drain junction for fast programming and FN injection from the floating gate toward the source junction for erasure.
The main advantage of the stacked gate flash EEPROM cell is its small area, which makes it well-suited for high-density applications (so-called bulk memory). The main disadvantages of the stacked gate cell, however, are high processing complexity, high power consumption (in order to compensate for the intrinsically low programming efficiency), and a presence of major reliability problems (such as overerase, soft-write and short-channel effects, and drain disturb) that compromise its scalability especially for embedded applications. Additionally, a conventional NOR array configuration, which is the configuration commonly used for stacked-gate type memory, requires 1/2 contact per bit. This requirement limits the yield for a matrix of memory cells, particularly as the density of memories continues to increase.
Contactless array configurations have been proposed for stacked-gate EPROM and Flash memory cells such as that shown in FIG. 1. (See, e.g., J. Esquivel et al., IEDM technical digest p. 592, (1986)). Advantageously, using a contactless array configuration for stacked-gate cells can increase the memory density significantly. An example of one such contactless array configuration is the Alternate Metal Ground ("AMG") configuration, as described by B. Eitan et al., "Alternate Metal Virtual Ground (AMG)--a new scaling concept for very high density EPROM's," IEEE Electron Device Letters, Vol. 12, No. 8, 450 (August 1991).
The AMG configuration, which was first developed for EPROMs and later extended to Flash memory, is, however, only possible at the expense of a complicated bitline segmentation scheme and a lower programming and read-out speed. Further, a main problem with these contactless array concepts generally is the high channel current required for channel hot-electron programming, which limits performance due to parasitic bit-line resistance and source-line resistances.
Another class of flash EEPROMs uses bi-directional FN tunneling and is essentially derived from conventional FLOTOX EEPROMs. An example of such a bi-directional FN tunneling device is shown in FIG. 3. The main advantage of this cell is the very low power consumption that it requires for FN programming. Therefore, the programming voltages can be generated on-chip, and operation of the device requires only a single supply voltage.
The main disadvantages of these bi-directional FN tunneling devices, however, are the very high voltages (20 V) that need to be switched on-chip, and the corresponding reliability problems (such as oxide defects and junction breakdown), the large transistor area, and the low programming speed. While a smaller transistor area can be achieved, doing so will typically increase the processing complexity and reduce the gate coupling coefficient at the expense of even higher programming voltages. Additionally, while programming speed can be increased by using page-mode programming techniques, such techniques complicate circuit design. Further, the scalability of this cell concept is highly questionable, particularly because of limitations that exist with respect to tunnel oxide scaling.
A typical high-density configuration for these bidirectional FN tunneling memories is the NAND configuration, as shown, for instance, in FIG. 4. Unfortunately, however, this NAND configuration suffers from a very high access time on the order of microseconds. In addition, contactless array configurations have also been proposed for these devices, in an effort to maximize the array density in stand-alone memory devices. (See, e.g., M. Gill et al., "A 5 Volt Contactless Array 256K Bit Flash EEPROM Technology," Texas Instruments Inc., IEDM Technical Digest, 428 (1988)).
Still another class of flash EEPROMs take the form of asymmetrical flash memory transistors that use Source Side Injection (SSI) as a programming mechanism. An example of one such cell configuration, for instance, is disclosed by U.S. Pat. No. 5,212,541 (Bergemont), issued May 18, 1993 to National Semiconductor Corporation. The cell disclosed by Bergemont has a split-gate structure and includes (i) a first insulating silicon dioxide layer formed over the channel region between the source and drain, (ii) a polysilicon floating gate formed over the first insulating layer and extending from the drain to cover a first portion of the channel, (iii) a second silicon dioxide insulating layer formed over the floating gate, and (iv) a polysilicon control gate formed over the second insulating layer above the floating gate and having an access portion that extends above the remaining second portion of the channel over the first insulating layer. (See, e.g., Bergemont, at column 3, lines 26-55).
Once a transistor concept has been defined in a given process technology, it has to be designed in such a way that a practical memory organization is obtained. Moreover, the transistor properties have to be exploited in order to optimize the density of the resulting memory array or matrix, taking into account circuit-related parameters such as disturb conditions, delay times, read-out current and capacitive and resistive loads for the periphery circuits. Therefore, the basic layout of the transistor depends strongly on how different transistors are to be interconnected in a circuit. This is where the term "memory cell" comes in: a memory cell, as opposed to a memory transistor, is the practical layout of the transistor that is repeatedly copied through mirroring or translation along its symmetry axes in order to produce the full memory array or matrix.
The advantages of optimizing memory cells for contactless arrays in EPROM and EEPROM memories have long been recognized. For instance, Esquivel et al., "High Density Contactless, Self Aligned EPROM Cell Array Technology," IEDM 1986, describe this principle in a conventional EPROM array, while Gill et al., "A 5 Volt Contactless Array 256K Bit Flash EEPROM Technology", IEDM 1988, describe a similar contactless array for Flash memories.
It is also well known to those of ordinary skill in the art that asymmetrical Flash memory transistors, which often use source-side injection as a programming mechanism, are well-suited for the implementation in contactless arrays. Examples of such contactless arrays are disclosed, for instance, in the Bergemont patent described above, as well as in U.S Pat. No. 5,280,446, issued on Jan. 18, 1994 (Ma et al.) and U.S Pat. No. 5,284,784, issued Feb. 8, 1994 (Manley). In general, these contactless array configurations provide a separate control line for every column or row, which adds to surface area. While this area overhead can be largely relaxed by the use of an additional polysilicon layer, doing so would require the use of expensive and complicated triple polysilicon technology.
In addition, contactless arrays have other drawbacks as well. First, if the array is to have a common source architecture with dedicated bitlines, as shown in FIG. 6 for example, then the buried bitlines will limit the scalability of the cell, due to the necessary spacing rule between adjacent bitlines that cannot be scaled in proportion to the other cell dimensions. Second, even though source side hot-electron injection requires only moderate channel currents (compared to conventional drain side injection), voltage drops along the buried difflusion lines (especially the source line) can still deteriorate the read-out current and the access time, particularly in larger memories.
Furthermore, distributed contacts from active diffusion lines to metal have to be provided regularly (such as every 16 bits) in order to reduce the bit-line resistance and source line resistance. This adds to the overall size of the memory array, increasing the equivalent area per bit in addition to the contactless cell itself. In addition, this introduces asymmetry in the array, as the read-out current becomes a function of the distance between the considered cell and the closest contact. These uniformities have to be taken into account when designing the read-out circuitry, since the slowest bit will determine the access time of the memory.
In view of the deficiencies in the art, there is a need for an improved array of erasable and programmable semiconductor memories cells.